A Rotated Array Clustered Extended Hypercube Processor, the RACE-H Processor

The RACE-Hypercube Processor is a highly parallel signal processor with fourteen degrees of freedom in selecting parallel operations. The fourteen degrees of freedom include the ability to select the 1) number of very long instruction word (VLIW) slots, 2) number and type of application specific instructions, 3) number and type of application specific processing element (PE) hardware assists, 4) number of PEs, 5) operation as a single issue uni-processor, 6) operation as a variable-length indirect VLIW (iVLIW) uni-processor, 7) operating each PE as a single issue PE, 8) operating each PE as a variable-length iVLIW PE, 9) operation with 32-bit packed data, 10) operation with 64-bit packed data, 11) operation with parallel independent PE conditional execution, 12) type of PE-to-PE communications including single cycle concurrent mesh, torus, hypercube, hypercube-complement communications, 13) operation with independent PE threaded array operations, and 14) background operations on the scalable direct memory access (DMA). A brief description of the RACE-H architecture is provided along with a description of the scalable DMA subsystem, programming tools, and a brief performance evaluation. The RACE-Hypercube architecture allows the achievement of up to 1.024 trillion bytes/sec at a relatively low clock frequency of 250MHz with short execution unit pipelines and an architecture that is programmer friendly.